Power-efficient data management for dynamic applications

In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain

Power aware data and memory management for dynamic applications

In recent years, the semiconductor industry has turned its focus towards heterogeneous multiprocessor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility perfectly supports the emerging market of interactive, mobile data and content services. The platform’s performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads into account and do not deal with the dynamic behaviour of these novel applications. The main limitations of current techniques are outlined and an approach for dealing with them is introduced

An integrated hardware/software approach for run-time scratch-management

An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applications on the architecture. However, today’s embedded operating systems abstract away the precise architectural details of the platform. As a consequence, they cannot exploit the energy efficiency of scratchpad memories. We present in this paper a novel integrated hardware/software solution to support scratchpad memories at a high abstraction level. We exploit hardware support to alleviate the transfer cost from/to the scratchpad memory and at the same time provide a high-level programming interface for run-time scratchpad management. We demonstrate the effectiveness of our approach with a case-study

Autoantibodies against type I IFNs in patients with life-threatening COVID-19

Interindividual clinical variability in the course of severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) infection is vast. We report that at least 101 of 987 patients with life-threatening coronavirus disease 2019 (COVID-19) pneumonia had neutralizing immunoglobulin G (IgG) autoantibodies (auto-Abs) against interferon-w (IFN-w) (13 patients), against the 13 types of IFN-a (36), or against both (52) at the onset of critical disease; a few also had auto-Abs against the other three type I IFNs. The auto-Abs neutralize the ability of the corresponding type I IFNs to block SARS-CoV-2 infection in vitro. These auto-Abs were not found in 663 individuals with asymptomatic or mild SARS-CoV-2 infection and were present in only 4 of 1227 healthy individuals. Patients with auto-Abs were aged 25 to 87 years and 95 of the 101 were men. A B cell autoimmune phenocopy of inborn errors of type I IFN immunity accounts for life-threatening COVID-19 pneumonia in at least 2.6% of women and 12.5% of men

Case study: Definition and Pathfinding of a GPU

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Physical design implementation of segmented buses to reduce communication energy

The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, segmented buses have gained interest in the architectural community. However, the netlist topology and the physical design stage significantly influence the final communication energy cost. We present in this paper an automated way to implement a netlist consisting of hard macro blocks, which are interconnected with heavily segmented buses in an energy optimal fashion for communication. We optimize the network wires energy dissipation in two separate, but related steps: minimizing the number of segments for active communication paths at the first step (block ordering), followed by the activity aware floorplanning step to minimize the physical length of these segments. Energy gains of up to a factor of 4 are achieved compared to a standard system implementation using a shared bus. Especially, the block ordering step contributes significantly to the network energy optimization process

Pathfinding: a design methodology for fast exploration and optimisation of 3D-stacked integrated circuits

SOC 2009info:eu-repo/semantics/publishe

Pathfinding and TechTuning

This chapter discusses various implications of the 3D integration technology on the design methodologies, flows, and associated tools. The experiences from the advanced 2D technologies are extrapolated and combined with the incremental challenges posed by the 3D technologies, and the requirements for design ecosystem for 3D technologies are precipitated. The chapter is organized in five sections. In the first section, we define the overall requirements for the 3D design ecosystem, and we identify the need for two incremental design methodologies, in addition to the traditional design authoring flow. The second section describes one of the incremental design methodologies-named PathFinding, and the third section discusses the other methodology-named TechTuning. In section four we present practical application of the proposed design methodology and associated tool chain. Section 5 gives a brief summary and few concluding remarks. © 2011 Springer Science+Business Media, LLC.SCOPUS: ch.binfo:eu-repo/semantics/publishe

PathFinding - Determining the technology/design sweetspot

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